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1 ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. dsc-5711/4 idt72v70200 3.3 volt time slot interchange digital switch 512 x 512 idt, the idt logo are registered trademarks of integrated device technology, inc.
rx0 rx1 rx2 rx3 rx4 rx5 rx6 rx7 ode f0i v cc cs ds/ rd r/ w / wr a0-a7 gnd cco dta d8-d15/ ad0-ad7 rx8 rx9 rx10 rx11 rx12 rx13 rx14 rx15 tx0 tx1 tx2 tx3 tx4 tx5 tx6 tx7 tx8 tx9 tx10 tx11 tx12 tx13 tx14 tx15 as/ ale im clk fe ic tdi tms tck tdo trst reset ic 5711 drw01 receive serial data streams output mux loopback test port data memory internal registers microprocessor interface timing unit connection memory transmit serial data streams
? 512 x 512 channel non-blocking switching at 2.048 mb/s ? per-channel variable or constant throughput delay ? automatic identification of st-bus ? /gci interfaces ? accept 16 serial data streams of 2.048 mb/s ? automatic frame offset delay measurement ? per-stream frame delay offset programming ? per-channel high impedance output control ? per-channel processor mode ? control interface compatible to intel/motorola cpus ? connection memory block programming ? ieee-1149.1 (jtag) test port ? available in 84-pin plastic leaded chip carrier (plcc), 100-pin ball grid array (bga), 100-pin plastic quad flatpack (pqfp) and 100-pin thin quad flatpack (tqfp) ? 3.3v power supply ? operating temperature range -40 c to +85 c the idt72v70200 is a non-blocking digital switch that has a capacity of 512 x 512 channels at 2.048 mb/s. some of the main features are: program- mable stream and channel control, processor mode, input offset delay and high- impedance output control. per-stream input delay control is provided for managing large multi-chip switches that transport both voice channel and concatenated data channels. in addition, input streams can be individually calibrated for input frame offset.
2 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 index 5711 drw04 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 90 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dnc dnc dnc dnc rx0 rx1 rx2 rx3 rx4 rx5 rx6 rx7 rx8 rx9 rx10 rx11 rx12 rx13 rx14 rx15 fe/hclk gnd clk vcc cco
d15 d14 d13 d12 d11 d10 d9 d8 gnd vcc ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 gnd dnc dnc dnc dnc dnc dnc dnc tms tdi tdo tck ic ic a0 a1 a2 a3 a4 a5 a6 a7 ds/ r/ / as/ale im gnd tx15 tx14 tx13 tx12 tx11 tx10 tx9 tx8 vcc gnd tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 ode gnd dnc dnc dnc dnc dnc
tqfp: 0.50mm pitch, 14mm x 14mm (pn100-1, order code: pf; png100, order code: pfg) top view
3 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 symbol name i/o description gnd ground. ground rail. vcc vcc +3.3 volt power supply. tx0-15 (1) tx output 0 to 15 o serial data output stream. these streams have a data rate of 2.048 mb/s. (three-state outputs) rx0-15 (1) rx input 0 to 15 i serial data input stream. these streams have a data rate of 2.048 mb/s. f0i trst reset reset rd cs cs rd w wr w wr rd cs dta
4 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12
the idt72v70200 is capable of switching 512 x 512, 64 kbit/s pcm or n x 64 kbit/s channel data. the device maintains frame integrity in data applications and minimum throughput delay for voice applications on a per channel basis. the serial input streams of the idt72v70200 can have a bit rate of 2.048 mb/s and are arranged in 125 s wide frames, which contain 32 channels respectively. the data rates on input and output streams are identical. in processor mode, the microprocessor can access input and output time- slots on a per channel basis allowing for transfer of control and status information. the idt72v70200 automatically identifies the polarity of the frame synchroni- zation input signal and configures the serial streams to either st-bus ? or gci formats. with the variety of different microprocessor interfaces, idt72v70200 has provided an input mode pin (im) to help integrate the device into different microprocessor based environments: non-multiplexed or multiplexed. these interfaces provide compatibility with multiplexed and motorola non-multiplexed buses. the device can also resolve different control signals eliminating the use of glue logic necessary to convert the signals (r/ / , ds/ , as/ale). the frame offset calibration function allows users to measure the frame offset delay using a frame evaluation pin (fe). the input offset delay can be programmed for individual streams using internal frame input offset registers, see table 8. the internal loopback allows the tx output data to be looped around to the rx inputs for diagnostic purposes. a functional block diagram of the idt72v70200 is shown in figure 1. data and connection memory the received serial data is converted to parallel format by internal serial- to-parallel converters and stored sequentially in the data memory. the 8khz input frame pulse ( ) is used to generate channel and frame boundaries of the input serial data. depending on the interface mode select (ims) register, the usable data memory may be as large as 512 bytes. data to be output on the serial streams (tx0-15) may come from either the data memory or connection memory. for data output from data memory (connection mode), addresses in the connection memory are used. for data to be output from connection memory, the connection memory control bits must set the particular tx output in processor mode. one time-slot before the data is to be output, data from either connection memory or data memory is read internally. this allows enough time for memory access and parallel-to-serial conversion. connection and processor modes in the connection mode, the addresses of the input source data for all output channels are stored in the connection memory. the connection memory is mapped in such a way that each location corresponds to an output channel on the output streams. for details on the use of the source address data (cab and sab bits), see table 10. once the source address bits are programmed by the microprocessor, the contents of the data memory at the selected address are transferred to the parallel-to-serial converters and then onto a tx output stream. by having the each location in the connection memory specify an input channel, multiple outputs can specify the same input address. this can be a powerful tool used for broadcasting data. in processor mode, the microprocessor writes data to the connection memory. each location in the connection memory corresponds to a particular output stream and channel number and is transferred directly to the parallel-to- serial converter one time-slot before it is to be output. this data will be output on the tx streams in every frame until the data is changed by the microprocessor. as the idt72v70200 can be used in a wide variety of applications, the device also has memory locations to control the outputs based on operating mode. specifically, the idt72v70200 provides five per-channel control bits for the following functions: processor or connection mode, constant or variable delay, enables/three-state the tx output drivers and enables/disable the loopback function. in addition, one of these bits allows the user to control the cco output. if an output channel is set to a high-impedance state through the connection memory, the tx output will be in a high-impedance state for the duration of that channel. in addition to the per-channel control, all channels on the st-bus ? outputs can be placed in a high impedance state by either pulling the ode input pin low or programming the output stand-by (osb) bit in the interface mode selection register. this action overrides the per-channel programming in the connection memory bits. the connection memory data can be accessed via the microprocessor interface. the addressing of the devices internal registers, data and connection memories is performed through the address input pins and the memory select (ms) bit of the control register. for details on device addressing, see software control and control register bits description (table 3 and 5). serial data interface timing the master clock frequency must always be twice the data rate. for serial data rates of 2.048 mb/s, the master clock (clk) must be at 4.096 mhz. the input and output stream data rates will always be identical. the input 8 khz frame pulse can be in either st-bus ? or gci format. the idt72v70200 automatically detects the presence of an input frame pulse and identifies it as either st-bus ? or gci. in st-bus ? format, every second falling edge of the master clock marks a bit boundary and the data is clocked in on the rising edge of clk, three quarters of the way into the bit cell, see figure 7. in gci format, every second rising edge of the master clock marks the bit boundary and data is clocked in on the falling edge of clk at three quarters of the way into the bit cell, see figure 8. input frame offset selection input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment (i.e. ). although all input data comes in at the same speed, delays can be caused by variable path serial backplanes and variable path lengths which may be implemented in large centralized and distributed switching systems. because data is often delayed, this feature is useful in compensating for the skew between clocks. each input stream can have its own delay offset value by programming the frame input offset registers (for). the maximum allowable skew is +4.5 master clock (clk) periods forward with resolution of ? clock period. the output frame offset cannot be offset or adjusted. see figure 5, table 8 and 9 for delay offset programming. serial input frame alignment evaluation the idt72v70200 provides the frame evaluation (fe) input to determine different data input delays with respect to the frame pulse . a measurement cycle is started by setting the start frame evaluation (sfe) bit low for at least one frame. when the sfe bit in the ims register is changed from low to high, the evaluation starts. two frames later, the complete frame evaluation (cfe) bit of the frame alignment register (far) changes from low to high to signal that a valid offset measurement is ready to be read from bits 0
5 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 to 11 of the far register. the sfe bit must be set to zero before a new measurement cycle started. in st-bus ? mode, the falling edge of the frame measurement signal (fe) is evaluated against the falling edge of the st-bus ? frame pulse. in gci mode, the rising edge of fe is evaluated against the rising edge of the gci frame pulse. see table 7 and figure 4 for the description of the frame alignment register. memory block programming the idt72v70200 provides users with the capability of initializing the entire connection memory block in two frames. to set bits 11 to 15 of every connection memory location, first program the desired pattern in bits 5 to 9 of the ims register. the block programming mode is enabled by setting the memory block program (mbp) bit of the control register high. when the block programming enable (bpe) bit of the ims register is set to high, the block programming data will be loaded into the bits 11 to 15 of every connection memory location. the other connection memory bits (bit 0 to bit 10) are loaded with zeros. when the memory block programming is complete, the device resets the bpe bit to zero. loopback control the loopback control (lpbk) bit of each connection memory location allows the tx output data to be looped backed internally to the rx input for diagnostic purposes. if the lpbk bit is high, the associated tx output channel data is internally looped back to the rx input channel (i.e., data from tx n channel m routes to the rx n channel m internally); if the lpbk bit is low, the loopback feature is disabled. for proper per-channel loopback operation, the contents of frame delay offset registers must be set to zero. the switching of information from the input serial streams to the output serial streams results in a throughput delay. the device can be programmed to perform time-slot interchange functions with different throughput delay capabili- ties on the per-channel basis. for voice applications, variable throughput delay is best as it ensures minimum delay between input and output data. in wideband data applications, constant throughput delay is best as the frame integrity of the information is maintained through the switch. the delay through the device varies according to the type of throughput delay selected in the /c bit of the connection memory. variable delay mode ( v v v v v
6 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 connection memory control the cco pin is a 4.096 mb/s output, which carries 512 bits. the contents of the cco bit of each connection memory location are output on the cco pin once every frame. the contents of the cco bits of the connection memory are transmitted sequentially on to the cco pin and are synchronous with the data rates on the other serial streams. the cco bit is output one channel before the corresponding channel on the serial streams. for example, the contents of the cco bit in position 0 (tx0, ch0) of the connection memory is output on the first clock cycle of channel 31 through cco pin. the contents of the cco bit in position 32 (tx1, ch0) of the connection memory is output on the second clock cycle of channel 31 via cco pin. if the ode pin or the osb bit is high, the oe bit of each connection memory location controls the output drivers-enables (if high) or disables (if low). see table 4 for detail. the processor channel (pc) bit of the connection memory selects between processor mode and connection mode. if high, the contents of the connection memory are output on the tx streams. if low, the stream address bit (sab) and the channel address bit (cab) of the connection memory defines the source information (stream and channel) of the time-slot that will be switched to the output from data memory. the /c (variable/constant delay) bit in each connection memory location allows the per-channel selection between variable and constant throughput delay modes. if the lpbk bit is high, the associated tx output channel data is internally looped back to the rx input channel (i.e., rx n channel m data comes from the tx n channel m). if the lpbk bit is low, the loopback feature is disabled. for proper per-channel loopback operation, the contents of the frame delay offset registers must be set to zero.
after power up, the state of the connection memory is unknown. as such, the outputs should be put in high impedance by holding the ode low. while the ode is low, the microprocessor can initialize the device, program the active paths, and disable unused outputs by programming the oe bit in connection memory. once the device is configured, the ode pin (or osb bit depending on initialization) can be switched.
7 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 connection memory data memory 1 0 control register cr b 7 5711 drw06 10000000 the control register is only accessed when a7-a0 are all zeroed. when a7 =1, up to 32 bytes are randomly accessable via a0-a4 at any one instant. of which stream these bytes (channels) are accessed is determined by the state of cr b 3 -cr b 0. cr b 6cr b 5cr b 4cr b 2cr b 1cr b 0 cr b 4 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 stream cr b 2cr b 1cr b 0 0 0 0 0 0 0 0 0 cr b 3 cr b 3 8 9 10 11 12 13 14 15 000 001 010 011 100 101 110 111 1 1 1 1 1 1 1 1 channel 31 channel 31 channel 31 channel 31 channel 31 channel 31 channel 31 channel 31 channel 31 channel 31 channel 31 channel 31 channel 31 channel 31 channel 31 channel 31 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 10000001 10000010 10011111 external address bits a7-a0 figure 3. addressing internal memories
8 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 ? ? ?? ???? ?? ?? ???????? ?? ??? ?? ???? ?? ? ? ????
commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 "
# read/write address: 00 h , reset value: 0000 h . 1514131211109876543210 0000000000mbpms sta3 sta2 sta1 sta0 bit name description 15-6 unused must be zero for normal operation. 5 mbp when 1, the connection memory block programming feature is ready for the programming of connection (memory block program) memory high bits, bit 11 to bit 15. when 0, this feature is disabled. 4 ms when 0, connection memory is selected for read or write operations. when 1, the data memory is selected (memory select) for read operations and connection memory is selected for write operations. (no microprocessor write operation is allowed for the data memory.) 3-0 sta3-0 the binary value expressed by these bits refers to the input or output data stream, which corresponds (stream address bits) to the subsection of memory made accessible for subsequent operations. (sta3 = msb, sta0 = lsb) read/write address: 01 h , reset value: 0000 h . bit name description 15-10 unused must be zero for normal operation. 9-5 bpd4-0 these bits carry the value to be loaded into the connection memory block whenever the memory block (block programming data) programming feature is activated. after the mbp bit in the control register is set to 1 and the bpe bit is set to 1, the contents of the bits bpd4-0 are loaded into bit 15 to 11 of the connection memory. bit 10 to bit 0 of the connection memory are set to 0. 4 bpe a zero to one transition of this bit enables the memory block programming function. the bpe and (begin block programming bpd4-0 bits in the ims register have to be defined in the same write operation. once the bpe bit is set enable) high, the device requires two frames to complete the block programming. after the programming function has finished, the bpe bit returns to zero to indicate the operation is completed. when the bpe = 1, the bpe or mbp can be set to 0 to ensure proper operation. when bpe = 1, the other bit in the ims register must not be changed for two frames to ensure proper operation. 3 osb when ode = 0 and osb = 0, the output drivers of tx0 to tx15 are in high impedance mode. when (output stand by) ode= 0 and osb = 1, the output driver of tx0 to tx15 function normally. when ode = 1, tx0 to tx15 output drivers function normally. 2 sfe a zero to one transition in this bit starts the frame evaluation procedure. when the cfe bit in the far (start frame evaluation) register changes from zero to one, the evaluation procedure stops. to start another fame evaluation cycle, set this bit to zero for at least one frame. 1-0 unused must be zero for normal operation. 1514131211109876543210 000000 bpd4 bpd3 bpd2 bpd1 bpd0 bpe osb sfe 0 0 9
10 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 ??? ? ??? ? bit name description 15-13 unused must be zero for normal operation. 12 cfe when cfe = 1, the frame evaluation is completed and bits fd10 to fd0 bits contains a valid frame alignment (complete frame evaluation) offset. this bit is reset to zero, when sfe bit in the ims register is changed from 1 to 0. 11 fd11 the falling edge of fe (or rising edge for gci mode) is sampled during the clk-high phase (fd11 = 1) (frame delay bit 11) or during the clk-low phase (fd11 = 0). this bit allows the measurement resolution to ? clk cycle. 10-0 fd10-0 the binary value expressed in these bits refers to the measured input offset value. these bits are rest to (frame delay bits) zero when the sfe bit of the ims register changes from 1 to 0. (fd10 ? msb, fd0 ? lsb) read/write address: 02 h , reset value: 0000 h . 1514131211109876543210 0 0 0 cfe fd11 fd10 fd9 fd8 fd7 fd6 fd5 fd4 fd3 fd2 fd1 fd0
11 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 $ ??? ? ? ?? f0i
12 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 st-bus ? ?? ?? ?? ? ???????????? ??? figure 5. examples for input offset delay timing measurement result from corresponding input stream frame delay bits offset bits offset fd11 fd2 fd1 fd0 ofn2 ofn1 ofn0 dlen no clock period shift (default) 1000000 0 + 0.5 clock period shift 0000000 1 + 1.0 clock period shift 1001001 0 + 1.5 clock period shift 0001001 1 + 2.0 clock period shift 1010010 0 + 2.5 clock period shift 0010010 1 + 3.0 clock period shift 1011011 0 + 3.5 clock period shift 0011011 1 + 4.0 clock period shift 1100100 0 + 4.5 clock period shift 0100100 1
13 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 ?? v t
14 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 * the idt72v70200 jtag interface conforms to the boundary-scan stan- dard ieee-1149.1. this standard specifies a design-for-testability technique called boundary-scan test (bst). the operation of the boundary-scan circuitry is controlled by an external test access port (tap) controller. test access port (tap) the test access port (tap) provides access to the test functions of the idt72v70200. it consists of three input pins and one output pin. test clock input (tck) tck provides the clock for the test logic. the tck does not interfere with any on-chip clock and thus remain independent. the tck permits shifting of test data into or out of the boundary-scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. test mode select input (tms) the logic signals received at the tms input are interpreted by the tap controller to control the test operations. the tms signals are sampled at the rising edge of the tck pulse. this pin is internally pulled to vcc when it is not driven from an external source. test data input (tdi) serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the tms input. both registers are described in a subsequent section. the received input data is sampled at the rising edge of tck pulses. this pin is internally pulled to vcc when it is not driven from an external source. test data output (tdo) depending on the sequence previously applied to the tms input, the contents of either the instruction register or data register are serially shifted out towards the tdo. the data out of the tdo is clocked on the falling edge of the tck pulses. when no data is shifted through the boundary scan cells, the tdo driver is set to a high impedance state. test reset ( ) reset the jtag scan structure. this pin is internally pulled to vcc. instruction register in accordance with the ieee 1149.1 standard, the idt72v70200 uses public instructions. the idt72v70200 jtag interface contains a two-bit instruction register. instructions are serially loaded into the instruction register from the tdi when the tap controller is in its shifted-ir state. subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current, and to define the serial test data register path, which is used to shift data between tdi and tdo during data register scanning. see table below for instruction decoding. value instruction function 000 extest select boundary scan register 001 extest select boundary scan register 010 sample/preload select boundary scan register 011 sample/preload select boundary scan register 100 sample/preload select boundary scan register 101 sample/preload select boundary scan register 110 bypass select bypass register 111 bypass select bypass register jtag instruction register decoding test data register as specified in ieee 1149.1, the idt72v70200 jtag interface contains two test data registers: the boundary-scan register the boundary-scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the idt72v70200 core logic. the bypass register the bypass register is a single stage shift register that provides a one-bit path from tdi to its tdo. the idt72v70200 boundary scan register contains 118 bits. bit 0 in table 11 boundary scan register is the first bit clocked out. all three-state enable bits are active high.
15 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 ????? ? reset f0i dta cs w wr rd
16 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 note: 1. voltages are with respect to ground unless other wise stated. note: 1. outputs unloaded. 2. for tdi, tms, and trst pins, the maximum leakage current is 50 a. test point output pin c l gnd s 1 r l vcc gnd 5711 drw09 s 2 symbol characteristics min. typ. max. units i cc (1) supply current @ 2.048 mb/s 710ma i il (2) input leakage (input pins) 15 a i bl input leakage (i/o pins) 50 a c i input pin capacitance 10 pf i oz high-impedance leakage 5 a v oh output high voltage 2.4 v v ol output low voltage 0.4 v c o output pin capacitance 10 pf figure 6. output load s1 is open circuit except when testing output levels or high impedance states. s2 is switched to v cc or gnd when testing output levels or high impedance states. symbol parameter min. max. unit v cc supply voltage -0.3 5.0 v vi voltage on digital inputs gnd -0.3 5.5 v i o current at digital outputs 20 ma t s storage temperature -65 +125 c p d package power dissapation 1w note: 1. exceeding these values may cause permanent damage. functional operation under these conditions is not implied. + symbol parameter min. typ. max. units v cc positive supply 3.0 3.6 v v ih input high voltage (3.3v) 2.0 v cc v v ih input high voltage (5.0v) 2.0 5.5 v v il input low voltage gnd 0.8 v t op operating temperature -40 +85 c commercial
17 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 )
note: 1. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . symbol characteristics min. typ. max. units t fpw frame pulse width (st-bus ? , gci) bit rate = 2.048 mb/s 26 295 ns t fps frame pulse setup time before clk falling (st-bus ? or gci) 5 ns t fph frame pulse hold time from clk falling (st-bus ? or gci) 10 ns t cp clk period bit rate = 2.048 mb/s 190 300 ns t ch clk pulse width high bit rate = 2.048 mb/s 85 150 ns t cl clk pulse width low bit rate = 2.048 mb/s 85 150 ns t r , t f clock rise/fall time 10 ns symbol characteristics min. typ. max. unit test conditions t sis rx setup time 0 ns t sih rx hold time 10 ns t sod tx delay ? active to active 30 ns c l = 30pf 40 ns c l = 200pf t dz tx delay ? active to high-z 32 ns r l = 1k , c l = 200pf t zd tx delay ? high-z to active 32 ns r l = 1k , c l = 200pf t ode output driver enable (ode) delay 32 ns r l = 1k , c l = 200pf t xcd cco output delay 30 ns c l = 30pf 40 ns c l = 200pf )
18 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 t xcd t zd clk (st-bus ? ?? ?? note: 1. last channel = ch 31. note: 1. last channel = ch 31.
19 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 t alw address data t ads t adh ale 5711 drw14 t rw t ww t csrw t alrd t csr t csw t dhw t dhr t akh t ddr t dsw t swd t alwr t akd ad0-ad7 d8-d15
figure 11. multiplexed bus timing (intel mode) ) + note: 1. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . symbol parameter min. typ. max. units test conditions t alw ale pulse width 20 ns t ads address setup from ale falling 3 ns t adh address hold from ale falling 3 ns t alrd rd active after ale falling 3 ns t ddr data setup from dta low on read 5 ns c l = 150pf t csrw cs hold after rd / wr 5ns t rw rd pulse width (fast read) 45 ns t csr cs setup from rd 0ns t dhr (1) data hold after rd 10 20 ns c l = 150pf, r l = 1k t ww wr pulse width (fast write) 45 ns t alwr wr delay after ale falling 3 ns t csw cs setup from wr 0ns t dsw data setup from wr (fast write) 20 ns t swd valid data delay on write (slow write) 122 ns t dhw data hold after wr inactive 5 ns t akd acknowledgment delay: reading/writing registers 43/43 ns c l = 150pf reading/writing memory 760/750 ns c l = 150pf t akh (1) acknowledgment hold time 22 ns c l = 150pf, r l = 1k
20 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 ds 5711 drw15 address t css t dsh t asw t csh t ddr t ads t adh ad0-ad7 d8-d15 wr dta w f r s fr ff scs crr0sr0crseirsf symbol parameter min. typ. max. units test c onditions t asw ale pulse width 20 ns t ads address setup from as falling 3 ns t adh address hold from as falling 3 ns t ddr data setup from low on read 5 ns c l = 150pf t csh hold after ds falling 0 ns t css setup from ds rising 0 ns t dhw data hold after write 5 ns t dws data setup from ds ? write (fast write) 20 ns t swd valid data delay on write (slow write) 122 ns t rws r/ setup from ds rising 60 ns t rwh r/ hold from ds rising 5 ns t dhr (1) data hold after read 10 20 ns c l = 150pf, r l = 1k t dsh ds delay after as falling 10 ns t akd acknowledgment delay: reading/writing registers 43/43 ns c l = 150pf reading/writing memory 760/750 ns c l = 150pf t akh (1) acknowledgment hold time 22 ns c l = 150pf, r l = 1k note: 1. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l .
21 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 valid write address a0-a7 t css t csh r/ t rws t rwh t ads t adh valid write data ad0-ad7/ d8-d15 t dsw t dhw
t akd t akh t css t csh t rws t rwh valid read address t ads t adh valid read data t ddr t dhr t akd t akh 5711 drw16 t swd figure 13. motorola non-multiplexed asyncrounous bus timing )) + symbol parameter min. typ. max. units test conditions t css cs setup from ds falling 0 ns t rws r/w setup from ds falling 10 ns t ads address setup from ds falling 2 ns t csh cs hold after ds rising 0 ns t rwh r/w hold after ds rising 2 ns t adh address hold after ds rising 2 ns t ddr data setup from dta low on read 2 ns c l = 150pf t dhr data hold on read 10 20 ns c l = 150pf, r l = 1k t dsw data setup on write (fast write) 0 ns t swd valid data delay on write (slow write) 122 ns t dhw data hold on write 5 ns t akd acknowledgment delay: reading/writing registers 43/43 ns c l = 150pf reading/writing memory 760/750 ns c l = 150pf t akh (1) acknowledgment hold time 22 ns c l = 150pf, r l = 1k note: 1. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l .
22 commercial temperature range idt72v70200 3.3v time slot interchange digital switch 512 x 5 12 5711 drw17 ad0-ad7/ d8-d15 cs dta w ds r
23 corporate headquarter for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 408-330-1753 santa clara, ca 95054 fax: 408-492-8674 email: fifoh elp@idt.com www.idt.com 5711 drw18 xxxxxx idt device type x package process/ temperature range xx blank commercial (-40 c to +85 c) 72v70200 512 x 512 3.3v time slot interchange digital switch pfg pf green thin quad flat pack (tqfp, png100) thin quad flat pack (tqfp, pn100-1)
5/19/2000 pgs. 1, 3, 17 and 23. 8/15/2000 pgs. 1, 2, 3, 5, 12 and 23. 9/22/2000 pgs. 3, 12 and 17. 1/04/2001 pgs. 6, 11, 17, 19, 20, 21 and 22. 1/25/2001 pgs. 17 and 22. 08/06/2001 pgs. 4, 10, 15, and 22. 10/06/2008 pgs. 2, 3, 9, and 23.

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